1 Field of the Invention
The present invention generally relates to electronic design automation. More specifically, the present invention relates to methods and apparatuses for generating a transistor-level description of a portion of a circuit.
2 Related Art
Rapid advances in computing technologies have been made possible by advances in design and verification tools, because, without such tools, it would have been almost impossible to design and verify complicated integrated circuits which are commonly found in today's computing devices.
Unlike simulation-based techniques, STA (static timing analysis) verifies timing by computing the worst-case delays without enumerating all possible paths. Since STA does not enumerate all possible paths, STA can perform a thorough timing analysis for large integrated circuits within a reasonable amount of time.
Although an STA tool can quickly analyze a large number of paths, the delay values generated by the STA tool are usually not as accurate as those generated by a transistor-level simulator. Hence, it is generally desirable to improve the accuracy of STA tools by enabling them to leverage transistor-level simulation.